In the design and manufacture of ICs, such as Application-Specific ICs (ASICs), Radio Frequency ICs (RFICs), and digital logic in general, it is advantageous to minimize the number of pins on an IC's package. Reducing the pin-out in an IC device simplifies routing in the IC, minimizes the PCB area used, and reduces the package cost of the device. However, IC designers (e.g., ASIC or RFIC designers) have to include functionality that provides visibility to the internal signals of the IC, so that these signals can be used, for example, during post-silicon verification or for debug purposes. In this regard, the more internal signals that can be made visible, the greater the test flexibility that can be provided for verification and debug of the IC. In fact, the importance of visibility has increased significantly, in view of the increased mask costs of the existing IC process nodes. For example, if a fault goes undetected during the pre-silicon verification process, and remains undetected during the first spin of the device, it is absolutely essential that the maximum visibility possible be provided to ensure that the underlying issue is readily understood and the fault is eliminated prior to the second and (hopefully) final spin. As such, a situation may be imagined where a bug is present in the first spin of a device, but not enough visibility is provided to determine the location (or cause) of the bug. Consequently, the designers of the device are faced with the unfortunate dilemma of having to perform a multi-million dollar re-spin, and not having enough data to determine and correct the problem.
A typical visibility technique currently used is to provide a combinatorial multiplexer that selects which internal signals are visible on a visibility bus. For an RFIC, a typical design requirement is to provide visibility for the In-phase and Quadrature (I/Q) components of a signal, and adequate clock and control signal visibility to enable sampling of the data involved. Consequently, the visibility bus for a typical RFIC needs to have 18 bits for the I signal component, another 18 bits for the Q signal component, one bit for the clock, one bit for synchronization, or a total of 38 bits. Unfortunately, in the wireless terminal RFIC design field, reserving 38 bits during the operation of an RFIC for potential verification or debug purposes is prohibitive, because of the existing RFIC design requirements for small PCB footprints and low package costs.
Another visibility technique currently used is to multiplex multiple signals in a time-shared fashion to the visibility pins. For example, if a designer desires visibility for 24 signals in a device, but the device only has 4 pins available, the visibility logic can be designed to output the 24 signals sequentially in 4-bit groups. Unfortunately, in this example, the output clock rate would have to be six times that of the data rate of the signals the designer wishes to observe in the device. This design would require either an unrealistically high Input/Output (I/O) rate, or the designer would lose all visibility for signals that change faster than once every six clocks. Therefore, it would be desirable to have a flexible visibility technique, which enables an IC designer to tradeoff data rates for visibility resolution in a way that maximizes visibility and minimizes pin usage (and package cost) for the device involved.